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w78e54 8-bit microcontroller publication release date: november 1997 - 1 - revision a2 general description the w78e54 is an 8-bit microcontroller that is functionally compatible with the w78c54, except that the mask rom is replaced by a flash eeprom with a size of 16 kb. to facilitate programming and verification, the flash eeprom inside the w78e54 allows the program memory to be programmed and read electronically. once the code is confirmed, the user can protect the code for security. t he w78e54 microcontroller supplies a wider frequency range than most 8-bit microcontrollers on the market. it is functionally compatible with the industry-standard 80c52 microcontroller series, except that o ne extra 4-bit bit-addressable i/o port (port 4) and two additional external interrupts ( int2 , int3 ). the w78e54 contains four 8-bit bidirectional and bit-addressable i/o ports, three 16-bit timer/counters, and a serial port. these peripherals are supported by a eight-source, two-level interrupt capability. there are 256 bytes of ram and an 16 kb flash eeprom for application programs. the w78e54 microcontroller has two power reduction modes, idle mode and power-down mode, both of which are software selectable. the idle mode turns off the processor clock but allows for continued peripheral operation. the power-down mode stops the crystal oscillator for minimum power consumption. the external clock can be stopped at any time and in any state without affecting the processor. features 8-bit cmos microcontroller fully static design low standby current at full supply voltage dc-40 mhz operation 256 bytes of on-chip scratchpad ram 16 kb electrically erasable/programmable eprom 64 kb program memory address space 64 kb data memory address space four 8-bit bidirectional ports one extra 4-bit bit-addressable i/o port, additional int2 / int3 (available on 44-pin plcc/qfp package) three 16-bit timer/counters one full duplex serial port boolean processor eight-source, two-level interrupt capability built-in power management code protection mechanism packages: - dip 40: w78e54-16/24/40 - plcc 44: w78e54p-16/24/40 - qfp 44: W78E54F-16/24/40 - tqfp 44: w78e54m-16/24/40
w78e54 - 2 - pin configurations vcc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 39 40 34 35 36 37 38 30 31 32 33 26 27 28 29 21 22 23 24 25 p0.0, ad0 p0.1, ad1 p0.2, ad2 p0.3, ad3 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.5, a13 p2.6, a14 p2.7, a15 p2.0, a8 p2.1, a9 p2.2, a10 p2.3, a11 p2.4, a12 t2, p1.0 40-pin dip (w78e54) p1.2 p1.3 p1.4 p1.5 p1.6 rxd, p3.0 txd, p3.1 p1.7 rst int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 wr, p3.6 rd, p3.7 xtal1 xtal2 vss t2ex, p1.1 44-pin plcc (w78e54p) 44-pin qfp/tqfp (w78e54f/w78e54m)) 34 40 39 38 37 36 35 44 43 42 41 33 32 31 30 29 28 27 26 25 24 23 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 22 21 20 19 18 17 16 15 14 13 12 11 4 3 2 1 8 7 6 5 10 9 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v c c a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 40 2 1 44 43 42 41 6 5 4 3 39 38 37 36 35 34 33 32 31 30 29 p0.4, ad4 p0.5, ad5 p0.6, ad6 p0.7, ad7 ea ale psen p2.7, a15 p2.6, a14 p2.5, a13 28 27 26 25 24 23 22 21 20 19 18 17 10 9 8 7 14 13 12 11 16 15 p1.5 p1.6 p1.7 rst rxd, p3.0 txd, p3.1 int0, p3.2 int1, p3.3 t0, p3.4 t1, p3.5 a d 3 , p 0 . 3 t 2 , p 1 . 0 p 1 . 2 v c c a d 2 , p 0 . 2 a d 1 , p 0 . 1 a d 0 , p 0 . 0 t 2 e x , p 1 . 1 p 1 . 3 p 1 . 4 x t a l 1 v s s p 2 . 4 , a 1 2 p 2 . 3 , a 1 1 p 2 . 2 , a 1 0 p 2 . 1 , a 9 p 2 . 0 , a 8 x t a l 2 p 3 . 7 , / r d p 3 . 6 , / w r p 4 . 0 / i n t 3 , p 4 . 2 p4.1 p4.1 p 4 . 0 int2, p4.3 int2, p4.3 / i n t 3 , p 4 . 2
w78e54 publication release date: november 1997 - 3 - revision a2 pin description the w78e54 has two operating modes, normal and flash. in normal mode, the w78e54 corresponds to the w78c54. in flash mode, the user (the maker of the flash eeprom writer) can access the flash eeprom. p0.7 - p0.0 port 0, bits 7 - 0 mode description normal port 0, bits 0 through 7. port 0 is a bidirectional i/o port. this port also provides a multiplexed low order address/data bus during accesses to external memory. flash this port provides the data bus during access to the flash eeprom. p1.7 - p1.0 port 1, bits 7 - 0 mode description normal port 1, bits 0 through 7. port 1 is a bidirectional i/o port with internal pull-ups. pins p1.0 and p1.1 also serve as t2 (timer 2 external input) and t2ex (timer 2 capture/reload trigger), respectively. flash this port provides the low-order address bus during access to the flash eeprom. p2.7 - p2.0 port 2, bits 7 - 0 mode description normal port 2, bits 0 through 7. port 2 is a bidirectional i/o port with internal pull-ups. this port also provides the upper address bits for accesses to external memory.. flash this port provides the high-order address bus during access to the flash eeprom. p3.7 - p3.0 port 3, bits 7 - 0 mode description normal port 3, bits 0 through 7. port 3 is a bidirectional i/o port with internal pull-ups. all bits have alternate functions. flash p3.3 - p3.0 and p3.7 - p3.6 are the flash mode configuration pins, input. p3.3 - p3.0 and p3.7 - p3.6 are configured to select or execute the flash operations. for details, see flash operations . p4.3 - p4.0 port 4, bits 3 - 0 (available on 44-pin plcc/qfp package) mode description normal another bit-addressable bidirectional i/o port p4. p4.3 and p4.2 are alternative function pins. it can be used as general i/o pins or external interrupt input sources ( int2 / int3 ).
w78e54 - 4 - flash no function in this mode. ea/v pp mode description normal ea , external access, input, active low. this pin forces the processor to execute a program from the external rom. when the internal flash eeprom is accessed as in the w78c54, this pin should be kept high. flash v pp , program power supply pin, input. this pin accepts the high voltage (12v) needed for programming the flash eeprom. rst mode description normal rst, reset, input, active high. this pin resets the processor. it must be kept high for at least two machine cycles in order to be recognized by the processor. flash flash mode configuration pin, input, active high. rst is used to configure the flash operations. for details, see flash operations . ale mode description normal ale, address latch enable, output, active high. ale is used to enable the address latch that separates the address from the data on port 0. ale runs at 1/6th of the oscillator frequency. a single ale pulse is skipped during external data memory accesses. ale goes to a high impedance state with a weak pull-up during reset state. flash flash mode configuration pin, input, active low. ale is used to configure the flash operations. for details, see flash operations . psen mode description normal psen , program store enable, output, active low. this pin enables the external rom onto the port 0 address/data bus during fetch and movc operations. psen goes to a high impedance state with a weak pull-up during reset state flash flash mode configuration pin, input, active high. psen is used to configure the flash operations. for details, see flash operations. xtal1 mode description
w78e54 publication release date: november 1997 - 5 - revision a2 normal crystal 1. this is the crystal oscillator input. this pin may be driven by an external clock. flash connect to v ss . xtal2 mode description normal crystal 2. this is the crystal oscillator output. it is the inversion of xtal1. flash no function in this mode. v ss , v cc power supplies. these are the chip ground and positive supplies. block diagram
w78e54 - 6 - p3.0 ~ p3.7 p1.0 ~ p1.7 alu port 0 latch port 1 latch timer 1 timer 0 timer 2 port 1 uart xtal1 psen ale vss vcc rst xtal2 oscillator interrupt psw instruction decoder & sequencer reset block bus & clock controller sfr ram address power control 256 bytes ram & sfr stack pointer b addr. reg. incrementor pc dptr temp reg. t2 t1 acc port 3 latch port 4 latch port 3 port 2 latch p4.0 ~ p4.3 port 4 port 0 port 2 p2.0 ~ p2.7 p0.0 ~ p0.7 int2 int3
w78e54 publication release date: november 1997 - 7 - revision a2 functional description the w78e54 architecture consists of a core controller surrounded by various registers, five general purpose i/o ports, 256 bytes of ram, three timer/counters, and a serial port. the processor supports 111 different opcodes and references both a 64k program address space and a 64k data storage space. timers 0, 1, and 2 timers 0, 1, and 2 each consist of two 8-bit data registers. these are called tl0 and th0 for timer 0, tl1 and th1 for timer 1, and tl2 and th2 for timer 2. the tcon and tmod registers provide control functions for timers 0 and 1. the t2con register provides control functions for timer 2. rcap2h and rcap2l are used as reload/capture registers for timer 2. the operations of timer 0 and timer 1 are the same as in the w78c51. timer 2 is a special feature of the w78e54: it is a 16-bit timer/counter that is configured and controlled by the t2con register. like timers 0 and 1, timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit c/t2 in t2con. timer 2 has three operating modes: capture, auto- reload, and baud rate generator. the clock speed at capture or auto-reload mode is the same as that of timers 0 and 1. clock the w78e54 is designed to be used with either a crystal oscillator or an external clock. internally, the clock is divided by two before it is used. this makes the w78e54 relatively insensitive to duty cycle variations in the clock. crystal oscillator the w78e54 incorporates a built-in crystal oscillator. to make the oscillator work, a crystal must be connected across pins xtal1 and xtal2. in addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from xtal1 to xtal2 to provide a dc bias when the crystal frequency is above 24 mhz. external clock an external clock should be connected to pin xtal1. pin xtal2 should be left unconnected. the xtal1 input is a cmos-type input, as required by the crystal oscillator. as a result, the external clock signal should have an input one level of greater than 3.5 volts. power management idle mode the idle mode is entered by setting the idl bit in the pcon register. in the idle mode, the internal clock to the processor is stopped. the peripherals and the interrupt logic continue to be clocked. the processor will exit idle mode when either an interrupt or a reset occurs. power-down mode
w78e54 - 8 - when the pd bit of the pcon register is set, the processor enters the power-down mode. in this mode all of the clocks are stopped, including the oscillator. the only way to exit power-down mode is by a reset.
w78e54 publication release date: november 1997 - 9 - revision a2 reset the external reset signal is sampled at s5p2. to take effect, it must be held high for at least two machine cycles while the oscillator is running. an internal trigger circuit in the reset line is used to deglitch the reset line when the w78e54 is used with an external rc network. the reset logic also has a special glitch removal circuit that ignores glitches on the reset line. during reset, the ports are initialized to ffh, the stack pointer to 07h, pcon (with the exception of bit 4) to 00h, and all of the other sfr registers except sbuf to 00h. sbuf is not reset. option setting users write programs into the w78e54 by using the winbond proprietary writer. the writer programs the data into an internal 16 kb region and reads the data back for verification. after confirming that the program is correct, the user can lock the data so that they can no longer be read. lock bit this bit is used to protect the customer data in the w78e54. it may be turned on after the programmer finishes the programming and verify sequence. once this bit is set to logic 0, no flash data can be accessed again. movc execute this bit is used to restrict the region accessible to the movc instruction. it can prevent the program from being downloaded using this instruction if the program needs to jump outside to get data. when this bit is set to logic 0, a movc instruction in external program memory space will be able to access code in the external memory, but it will not be able to access code in the internal memory. a movc instruction in internal program memory space will always be able to access code in both internal and external memory. if this bit is logic 1, there are no restrictions on the movc instruction. new defined peripheral in order to be more suitable for i/o, an extra 4-bit bit-addressable port p4 and two external interrupt int2 , int3 has been added to either the plcc or qfp 44 pin package. and description follows: 1. int2/ int3 two additional external interrupts, int2 and int3 , whose functions are similar to those of external interrupt 0 and 1 in the standard 80c52. the functions/status of these interrupts are determined/shown by the bits in the xicon (external interrupt control) register. the xicon register is bit-addressable but is not a standard register in the standard 80c52. its address is at 0c0h. to set/clear bits in the xicon register, one can use the "setb (/clr) bit" instruction. for example, "setb 0c2h" sets the ex2 bit of xicon. ***xicon - external interrupt control (c0h) px3 ex3 ie3 it3 px2 ex2 ie2 it2
w78e54 - 10 - px3: external interrupt 3 priority high if set ex3: external interrupt 3 enable if set ie3: if it3 = 1, ie3 is set/cleared automatically by hardware when interrupt is detected/serviced it3: external interrupt 3 is falling-edge/low-level triggered when this bit is set/cleared by software px2: external interrupt 2 priority high if set ex2: external interrupt 2 enable if set ie2: if it2 = 1, ie2 is set/cleared automatically by hardware when interrupt is detected/serviced it2: external interrupt 2 is falling-edge/low-level triggered when this bit is set/cleared by software eight-source interrupt informations: interrupt source vector address polling sequence within priority level enable required settings interrupt type edge/level external interrupt 0 03h 0 (highest) ie.0 tcon.0 timer/counter 0 0bh 1 ie.1 - external interrupt 1 13h 2 ie.2 tcon.2 timer/counter 1 1bh 3 ie.3 - serial port 23h 4 ie.4 - timer/counter 2 2bh 5 ie.5 - external interrupt 2 33h 6 xicon.2 xicon.0 external interrupt 3 3bh 7 (lowest) xicon.6 xicon.3 2. port4 another bit-addressable port p4 is also available and only 4 bits (p4<3:0>) can be used. this port address is located at 0d8h with the same function as that of port p1, except the p4.3 and p4.2 are alternative function pins. it can be used as general i/o pins or external interrupt input sources ( int2 , int3 ). example: p4 reg 0d8h mov p4, #0ah ; output data "a" through p4.0 - p4.3. mov a, p4 ; read p4 status to accumulator. setb p4.0 ; set bit p4.0 clr p4.1 ; clear bit p4.1 3. reduce emi emission because of the large on-chip flash eeprom, when a program is running in internal rom space, the ale will be unused. the transition of ale will cause noise, so it can be turned off to reduce the emi emission if it is useless. turning off the ale signal transition only requires setting the bit 0 of the
w78e54 publication release date: november 1997 - 11 - revision a2 auxr sfr, which is located at 08eh. when ale is turned off, it will be reactivated when the program accesses external rom/ram data or jumps to execute an external rom code. the ale signal will turn off again after it has been completely accessed or the program returns to internal rom code space.. the ao bit in the auxr register, when set, disables the ale output. ***auxr - auxiliary register (8eh) - - - - - - - ao ao: turn off ale output. 4. power-off flag ***pcon - power control (87h) smod - - pof gf1 gf0 pd idl smod: double baud rate bit. when set to a 1, the baud rate is dou bled when the serial port is being used in either modes 1, 2, 3. pof: power off flag. bit is set by hardware when power on reset. it can be cleared by software to determine chip reset is a warm boot or cold boot. gf1, gf0: these two bits are general-purpose flag bits for the user. pd: power down mode bit. set it to enter power down mode. idl: idle mode bit. set it to enter idle mode. the power-off flag is located at pcon.4. this bit is set when v dd has been applied to the part. it can be used to determine if a reset is a warm boot or a cold boot if it is subsequently reset by software. flash operations in normal operation, the w78e54 is functionally compatible with the w78c54. in the flash operating mode, the flash eeprom can be programmed and verified repeatedly. once the code inside the flash eeprom is confirmed, the code can be protected. the flash eeprom and the operations on it are described below. all of the operations are configured by the pins rst, ale, psen , a9ctrl (p3.0), a13ctrl (p3.1), a14ctrl (p3.2), oectrl (p3.3), ce (p3.6), oe (p3.7), a0 (p1.0) and v pp ( ea ). in these operations, a15 to a0 (p2.7 to p2.0, p1.7 to p1.0) and d7 to d0 (p0.7 to p0.0) serve as the address and data bus, respectively. read operation this operation enables customers to read their codes and the option bits. the data will not be valid if the lock bit is programmed to low.
w78e54 - 12 - program operation this operation is used to program data to the flash eeprom and the option bits. programming is initiated when v pp reaches v cp (12.5v) level, ce is set to low, and oe is set to high. program verify operation all data must be checked after programming. this operation should be performed after each byte is programmed, and it will ensure a substantial program margin. operation p3.0 (a9 ctrl) p3.1 (a13 ctrl) p3.2 (a14 ctrl) p3.3 (oe ctrl) p3.6 ( ce ) p3.7 ( oe ) ea (v pp ) p2, p1 (a15 to a0) p0 (d7 to d0) notes read v il v il v il v il v il v il v ih address data out 1, 2 program v il v il v il v il v il v ih v cp address data in 1, 2 program verify v il v il v il v il v ih v il v cp address data out 3 notes: 1. during all of these operations, rst = v ih , ale = v il, and psen = v ih . 2. v cp = 12v, v ih = v dd , v il = vss. 3. the program verify operation should follow the programming operaion. absolute maximum ratings parameter symbol min. max. unit dc power supply v dd - v ss -0.3 +7.0 v input voltage v in v ss -0.3 v dd +0.3 v operating temperature t a 0 70 c storage temperature t st -55 +150 c note: exposure to conditions beyond those listed under absolute maximum ratings may adversely affect the life and reliability of the device. p1 p3.0 p3.1 p3.2 p3.3 p3.6 p3.7 x'tal1 x'tal2 p0 ea/vpp ale rst psen p2 vss a0 to a7 v cp v il v ih v il v il v il v il v il a8 to a15 pgm data v ih v ih +5v programming configuration programming verification v dd p1 p3.0 p3.1 p3.2 p3.3 p3.6 p3.7 x'tal1 x'tal2 p0 ea/vpp ale rst psen p2 vss a0 to a7 v cp v il v ih v il v il v il v il v il a8 to a15 pgm data v ih v ih +5v v dd
w78e54 publication release date: november 1997 - 13 - revision a2 dc characteristics (v dd -v ss = 5v 10%, t a = 25 c, fosc = 20 mhz, unless otherwise specified.) parameter sym. specification unit test conditions min. max. operating voltage v dd 4.5 5.5 v operating current i dd - 20 ma no load v dd = 5.5v idle current i idle - 6 ma idle mode v dd = 5.5v power down current i pwdn - 50 m a power-down mode v dd = 5.5v input current p1, p2, p3, p4 i in1 -50 +10 m a v dd = 5.5v v in = 0v or v dd input current rst i in2 -10 +300 m a v dd = 5.5v 0 < v in < v dd input leakage current p0, /ea i lk -10 +10 m a v dd = 5.5v 0v w78e54 - 14 - dc characteristics, continued parameter sym. specification unit test conditions min. max. output low voltage p0, ale, psen [*3] v ol2 - 0.45 v v dd = 4.5v i ol = +4ma sink current p1, p2, p3, p4 i sk1 4 12 ma v dd = 4.5v vs = 0.45v sink current p0, ale, psen i sk2 10 20 ma v dd = 4.5v vs = 0.45v output high voltage p1, p2, p3, p4 v oh1 2.4 - v v dd = 4.5v i oh = -100 m a output high voltage p0, ale, psen [*3] v oh2 2.4 - v v dd = 4.5v i oh = -400 m a source current p1, p2, p3, p4 i sr1 -120 -250 m a v dd = 4.5v vs = 2.4v source current p0, ale, psen i sr2 -8 -14 ma v dd = 4.5v vs = 2.4v notes: 1. rst pin is a schmitt trigger input. rst has internal pull-low resistors of about 30 k w . 3. p0, ale and /psen are tested in the external access mode. 4. xtal1 is a cmos input. 5. pins of p1, p2, p3, p4 can source a transition current when they are being externally driven from 1 to 0. the transition current reaches its maximum value when v in approximates to 2v. ac characteristics the ac specifications are a function of the particular process used to manufacture the part, the ratings of the i/o buffers, the capacitive load, and the internal routing capacitance. most of the specifications can be expressed in terms of multiple input clock periods (t cp ), and actual parts will usually experience less than a 20 ns variation. the numbers below represent the performance expected from a 0.8 micron cmos process when using 2 and 4 ma output buffers. clock input waveform t t xtal1 f ch cl op, t cp
w78e54 publication release date: november 1997 - 15 - revision a2 parameter symbol min. typ. max. unit notes operating speed f op 0 - 40 mhz 1 clock period t cp 25 - - ns 2 clock high t ch 10 - - ns 3 clock low t cl 10 - - ns 3 notes: 1. the clock may be stopped indefinitely in either state. 2. the t cp specification is used as a reference in other specifications. 3. there are no duty cycle requirements on the xtal1 input. program fetch cycle parameter symbol min. typ. max. unit notes address valid to ale low t aas 1 t cp - d - - ns 4 address hold from ale low t aah 1 t cp - d - - ns 1, 4 ale low to psen low t apl 1 t cp - d - - ns 4 psen low to data valid t pda - - 2 t cp ns 2 data hold after psen high t pdh 0 - 1 t cp ns 3 data float after psen high t pdz 0 - 1 t cp ns ale pulse width t alw 2 t cp - d 2 t cp - ns 4 psen pulse width t psw 3 t cp - d 3 t cp - ns 4 notes: 1. p0.0 - p0.7, p2.0 - p2.7 remain stable throughout entire memory cycle. 2. memory access time is 3 t cp . 3. data have been latched internally prior to psen going high. 4. " d " (due to buffer driving delay and wire loading) is 20 ns. data read cycle parameter symbol min. typ. max. unit note s ale low to rd low t dar 3 t cp - d - 3 t cp + d ns 1, 2 rd low to data valid t dda - - 4 t cp ns 1 data hold from rd high t ddh 0 - 2 t cp ns data float from rd high t ddz 0 - 2 t cp ns rd pulse width t drd 6 t cp - d 6 t cp - ns 2 notes: 1. data memory access time is 8 t cp . 2. " d " (due to buffer driving delay and wire loading) is 20 ns.
w78e54 - 16 - data write cycle parameter symbol min. typ. max. unit ale low to wr low t daw 3 t cp - d - 3 t cp + d ns data valid to wr low t dad 1 t cp - d - - ns data hold from wr high t dwd 1 t cp - d - - ns wr pulse width t dwr 6 t cp - d 6 t cp - ns note: " d " (due to buffer driving delay and wire loading) is 20 ns. port access cycle parameter symbol min. typ. max. unit port input setup to ale low t pds 1 t cp - - ns port input hold from ale low t pdh 0 - - ns port output to ale t pda 1 t cp - - ns note: ports are read during s5p2, and output data becomes available at the end of s6p2. the timing data are referenced to ale, since it provides a convenient reference. program operation parameter symbol min. typ. max. unit v pp setup time t vps 2.0 - - m s data setup time t ds 2.0 - - m s data hold time t dh 2.0 - - m s address setup time t as 2.0 - - m s address hold time t ah 0 - - m s ce program pulse width for program operation t pwp 295 300 305 m s ce program pulse width for program operation t opwp 295 300 305 m s oectrl setup time t ocs 2.0 - - m s oectrl hold time t och 2.0 - - m s oe setup time t oes 2.0 - - m s oe high to output float t dfp 0 - 130 ns data valid from oe t oev - - 150 ns note: flash data can be accessed only in flash mode. the rst pin must pull in v ih status, the ale pin must pull in v il status, and the psen pin must pull in v ih status.
w78e54 publication release date: november 1997 - 17 - revision a2 timing waveforms program fetch cycle s1 xtal1 s2 s3 s4 s5 s6 s1 s2 s3 s4 s5 s6 ale port 2 a0-a7 a0-a7 data a0-a7 code t a0-a7 data code port 0 psen pdh, t pdz t pda t aah t aas t psw t apl t alw data read cycle s2 s3 s5 s6 s1 s2 s3 s4 s5 s6 s1 s4 xtal1 ale psen data a8-a15 port 2 port 0 a0-a7 rd t ddh, t ddz t dda t drd t dar
w78e54 - 18 - timing waveforms, continued data write cycle s2 s3 s5 s6 s1 s2 s3 s4 s1 s5 s6 s4 xtal1 ale psen a8-a15 data out port 2 port 0 a0-a7 wr t t daw dad t dwr t dwd port access cycle xtal1 ale s5 s6 s1 data out t t port input t sample pda pdh pds
w78e54 publication release date: november 1997 - 19 - revision a2 timing waveforms, continued program operation p2, p1 (a15... a0) address stable v ih v il address valid p3.6 (ce) v ih v il v ih v il v ih v il data in data out vpp d out read verify vcp v ih program program verify t vps t ds t dh t as t ah t pwp t oes t dfp t oev t ocs v ih v il t och p3.7 (oe) p0 (a7... a0) p3.3 (oectrl)
w78e54 - 20 - typical application circuits expanded external program memory and crystal ad0 a0 a0 a0 10 a1 9 a2 8 a3 7 a4 6 a5 5 a6 4 a7 3 a8 25 a9 24 a10 21 a11 23 a12 2 a13 26 a14 27 a15 1 ce 20 oe 22 o0 11 o1 12 o2 13 o3 15 o4 16 o5 17 o6 18 o7 19 27512 ad0 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 ad0 ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 p1.0 1 p1.1 2 p1.2 3 p1.3 4 p1.4 5 p1.5 6 p1.6 7 p1.7 8 39 38 37 36 35 34 33 32 21 22 23 24 25 26 27 28 17 wr p0.0 p0.1 p0.2 p0.3 p0.4 p0.5 p0.6 p0.7 p2.0 p2.1 p2.2 p2.3 p2.4 p2.5 p2.6 p2.7 rd 16 psen 29 ale 30 txd 11 rxd 10 w78e54 10 u 8.2 k cc crystal c1 c2 r ad1 ad2 ad3 ad4 ad5 ad6 ad7 a8 ad1 ad2 ad3 ad4 ad5 ad6 ad7 gnd a1 a2 a3 a4 a5 a6 a7 a1 a2 a3 a4 a5 a6 a7 a8 a9 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a10 a11 a12 a13 a14 a15 gnd a9 a10 a11 a12 a13 a14 a15 v cc v figure a crystal c1 c2 r 16 mhz 30p 30p - 24 mhz 15p 15p - 33 mhz 10p 10p 6.8k 40 mhz 5p 5p 4.7k above table shows the reference values for crystal applications. note: c1, c2, r components refer to figure a.
w78e54 publication release date: november 1997 - 21 - revision a2 typical application circuits, continued expanded external d ata memory and oscillator 10 u 8.2 k cc oscillator ea 31 xtal1 19 xtal2 18 rst 9 int0 12 int1 13 t0 14 t1 15 1 2 3 4 5 6 p1.0 p1.1 p1.2 p1.3 p1.4 p1.5 p1.6 7 p1.7 8 p0.0 39 p0.1 38 p0.2 37 p0.3 36 p0.4 35 p0.5 34 p0.6 33 p0.7 32 p2.0 21 p2.1 22 p2.2 23 p2.3 24 p2.4 25 p2.5 26 p2.6 27 p2.7 28 rd 17 wr 16 psen 29 ale 30 txd 11 rxd 10 w78e54 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 a0 a1 a2 a3 a4 a5 a6 a7 d0 3 q0 2 d1 4 q1 5 d2 7 q2 6 d3 8 q3 9 d4 13 q4 12 d5 14 q5 15 d6 17 q6 16 d7 18 q7 19 oc 1 g 11 74ls373 a0 a1 a2 a3 a4 a5 a6 a7 10 9 8 7 6 5 4 3 a0 a1 a2 a3 a4 a5 a6 a7 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 a8 a9 a10 a11 a12 a13 a14 25 24 21 23 26 1 20 2 a8 a9 a10 a11 a12 a13 a14 ce gnd a8 a9 a10 a11 a12 a13 a14 gnd 22 27 oe wr 20256 v cc v figure b package dimensions 40-pin dip seating plane 1. dimension d max. & s include mold flash or tie bar burrs. 2. dimension e1 does not include interlead flash. 3. dimension d & e1 include mold mismatch and are determined at the mold parting line. 6. general appearance spec. should be based on final visual inspection spec. . 1.372 1.219 0.054 0.048 notes: symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e a l s a a 1 2 e 0.050 1.27 0.210 5.334 0.010 0.150 0.016 0.155 0.018 0.160 0.022 3.81 0.406 0.254 3.937 0.457 4.064 0.559 0.008 0.120 0.670 0.010 0.130 0.014 0.140 0.203 3.048 0.254 3.302 0.356 3.556 0.540 0.550 0.545 13.72 13.97 13.84 17.01 15.24 14.986 15.494 0.600 0.590 0.610 2.286 2.54 2.794 0.090 0.100 0.110 b 1 1 e e 1 a 2.055 2.070 52.20 52.58 0 15 0.090 2.286 0.650 0.630 16.00 16.51 protrusion/intrusion. 4. dimension b1 does not include dambar 5. controlling dimension: inches. 15 0 e a a a c e base plane 1 a 1 e l a s 1 e d 1 b b 40 21 20 1 2
w78e54 - 22 - package dimensions, continued 44-pin plcc 44 40 39 29 28 18 17 7 6 1 l c 1 b 2 a h d d e b e h e y a a 1 seating plane d g g e symbol min. nom. max. max. nom. min. dimension in inches dimension in mm a b c d e h e l y a a 1 2 e b 1 h d g g d e notes: on final visual inspection spec. 4. general appearance spec. should be based 3. controlling dimension: inches protrusion/intrusion. 2. dimension b1 does not include dambar flash. 1. dimension d & e do not include interlead 0.020 0.145 0.026 0.016 0.008 0.648 0.590 0.680 0.090 0.150 0.028 0.018 0.010 0.653 0.610 0.690 0.100 0.050 bsc 0.185 0.155 0.032 0.022 0.014 0.658 0.630 0.700 0.110 0.004 0.508 3.683 0.66 0.406 0.203 16.46 14.99 17.27 2.296 3.81 0.711 0.457 0.254 16.59 15.49 17.53 2.54 1.27 4.699 3.937 0.813 0.559 0.356 16.71 16.00 17.78 2.794 0.10 bsc 16.71 16.59 16.46 0.658 0.653 0.648 16.00 15.49 14.99 0.630 0.610 0.590 17.78 17.53 17.27 0.700 0.690 0.680 q 44-pin qfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.254 0.101 0.010 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm a b c d e h d h e l y a a l 1 1 2 e 0.006 0.152 --- 0.002 0.075 0.01 0.081 0.014 0.087 0.018 1.90 0.25 0.05 2.05 0.35 2.20 0.45 0.390 0.025 0.063 0.003 0 7 0.394 0.031 0.398 0.037 9.9 0.80 0.65 1.6 10.00 0.8 10.1 0.95 0.398 0.394 0.390 0.530 0.520 0.510 13.45 13.2 12.95 10.1 10.00 9.9 7 0 0.08 0.031 0.01 0.02 0.25 0.5 --- --- --- --- --- q 2 q 0.025 0.036 0.635 0.952 0.530 0.520 0.510 13.45 13.2 12.95 0.051 0.075 1.295 1.905
w78e54 publication release date: november 1997 - 23 - revision a2 package dimensions, continued 44-pin tqfp seating plane 11 22 12 see detail f e b a y 1 a a l l 1 c e e h 1 d 44 h d 34 33 detail f 1. dimension d & e do not include interlead flash. 2. dimension b does not include dambar protrusion/intrusion. 3. controlling dimension: millimeter 4. general appearance spec. should be based on final visual inspection spec. 0.200 0.090 0.008 0.004 notes: symbol min. nom. max. max. nom. min. dimension in inch dimension in mm --- --- 0.047 0.002 0.037 0.0039 0.039 0.013 0.041 0.015 0.95 0.22 0.05 1.00 0.32 1.05 0.38 0.390 0.018 0.039 0.003 0 7 0.394 0.024 0.398 0.030 9.9 0.80 0.45 1.00 10.00 0.60 10.1 0.75 0.398 0.394 0.390 0.476 0.472 0.468 12.10 12.00 11.90 10.1 10.00 9.9 7 0 0.08 0.031 0.004 0.006 0.10 0.15 --- --- --- --- 1.20 a b c d e h d h e l y a a l 1 1 2 e q 2 q 0.025 0.036 0.635 0.952 0.476 0.472 0.468 12.10 12.00 11.90 --- --- --- --- headquarters no. 4, creation rd. iii, science-based industrial park, hsinchu, taiwan tel: 886-3-5770066 fax: 886-3-5792697 http://www.winbond.com.tw/ voice & fax-on-demand: 886-2-27197006 taipei office 11f, no. 115, sec. 3, min-sheng east rd., taipei, taiwan tel: 886-2-27190505 fax: 886-2-27197502 winbond electronics (h.k.) ltd. rm. 803, world trade square, tower ii, 123 hoi bun rd., kwun tong, kowloon, hong kong tel: 852-27513100 fax: 852-27552064 winbond electronics north america corp. winbond memory lab. winbond microelectronics corp. winbond systems lab. 2727 n. first street, san jose, ca 95134, u.s.a. tel: 408-9436666 fax: 408-5441798 note: all data and specifications are subject to change without notice.

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